HPC Memory Controller Write but can't Read

Jake,

Did a signal tap and local_init_done is asserted. Multiple writes work just fine.

ST shows the writes look great, all signals behaving as they should. On the reads though, as I indicated the, all activity stops the bus. Interesting observations though:

1. Correct data does appear on the read bus.

2. Local_read_req is normal operation.

3. Local_readdatavalid never asserts.

4. Local_ready, which my understanding is an invert of a slave waitrequest never deasserts during the first clock cycle of the read but stays asserted. My experience in other simulations is that there is always a single waitstate associated with reads.

I am doing simple basic read/write, 32-bit data, no bursting.

Thoughts?