Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi,
okay I got the example to work - using it under linux :) However my next problem is that my design is VHDL-based whereas the Avalon MM Master BFM is generated as Verilog (even if I request VHDL) and the ModelSim by Altera provides only support for one HDL --> I can't mix VHDL and Verilog. Any ideas how I can test my design? Current status is when I read from my slave it returns the data I've written to it just a few moments ago - although readdata is tied to a constant value ? Any Ideas? Thanks, Pete (p.s.: sorry for the long delay)