How to tackle memory bits wastage in STRATIX III in CODEC design?

I am involved in codec design for FPGA and ASIC platforms. Our design work involves a lot of data storage & our nature of data processing demands a lots of memory partioning, were some times width and depth of the memory is not powers of 2, so it leads to cosiderable amount of memory bits wastage, regarding this I have a doubts,

1. Do we have any kind of THUMB rule for "permissible percentage of memory bits that can be wasted w.r.t overall memory bits consumption" :confused:?

Thanks in advance,

Regards,

Mohankumar.Pandian