Forum Discussion
1 Reply
- Altera_Forum
Honored Contributor
If you are using the megafunction to generate DDR2 controller,
then modelsim testbench and memory model should have generated. That make life a lot easier.
Can anyone please help me to solve this problem?
I have compiled all the files successfully in modelsim. While simulating DDR2, the signals mem_dq and few other signals are undefined. Kindly explain the steps to simulate DDR2 IPcore Please help me...... Thanks & Regards VVIf you are using the megafunction to generate DDR2 controller,
then modelsim testbench and memory model should have generated. That make life a lot easier.