How to see the values of "Number of Address Pages/Size of Address Pages" in PCIe IP?

An address translation table entry is like a portal from an "block" of local avalon memory space to a "block" of memory the same size in the host.

You have to decide how many blocks of memory you need and set that number of table entries.

You then have to configure the table entries to do the mapping for you. The lower address bits define the position in the "block", the most significant

bits select the table entry, and so the mapping to the appropriate "block" in host memory, and vice versa.

That's from memory, but it should point you in the right direction.

Nial