How to run gate-level simulation for DDR2 SDRAM Controller

Hi jacklsw86,

Firstly, thank you for your comment.

I run synthesis the DDR2 controller and generate its post-fit model (.vo and .sdo file). When run this post-fit model with my testbench, the PLL block in the controller give the right output signal, but the others do not. Command signals to memory (like: mem_cs_n, mem_cas_n, mem_ras_n, mem_we_n,...) is not the same with functional simulation. In functional simulation, DDR2 Controller will automatically generate a sequence of commands that will initialize and calibration the memory. However, with gate simulation, the command remains at No Operation. It means that the initialization fails.

Can you talk more about timing constraints in SDC file? I think that we only need .vo and .sdo file to run gate-simulation. How to make the SDC file and put it into the testbench or .do file?