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Honored Contributor
Honored ContributorHow to "regenerate" an input clock if it's a burst clock
Hi guys, I have a Cyclone IV E and I have an external board which output a 27 Mhz clock with 8 bit data. The board at the end the chain needs to work another couple of signals (valid and sync) ...
Altera_ForumHonored Contributor
Honored ContributorApparently not required for the present problem, but it's possible to synchronize a clock over a limited frequency range (e.g. 500 or 1000 ppm) using PLL dynamic phase sift feature and respective user logic. This way you can e.g. implement soft CDR for source synchronous protocols with FPGA that don't have a respective hardware CDR feature.
