How to "regenerate" an input clock if it's a burst clock

Apparently not required for the present problem, but it's possible to synchronize a clock over a limited frequency range (e.g. 500 or 1000 ppm) using PLL dynamic phase sift feature and respective user logic. This way you can e.g. implement soft CDR for source synchronous protocols with FPGA that don't have a respective hardware CDR feature.