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Honored Contributor
Honored ContributorHow to "regenerate" an input clock if it's a burst clock
Hi guys, I have a Cyclone IV E and I have an external board which output a 27 Mhz clock with 8 bit data. The board at the end the chain needs to work another couple of signals (valid and sync) ...
Altera_ForumHonored Contributor
Honored ContributorHi Alex,
you need a continous (external) clock for your PLL. This PLL should create the 27MHz on your output. Use the incoming bursted 27MHz directly as clock input to latch the incoming 188byte. As the external and internal 27MHz are not phase aligned and may differ slightly in the frequency you need a fifo. RMII Ethernet Phys for example have similar functionality. Dirk
