How to reduce EMIF_USR_CLK frequêncy?

Hi there, folks

I am currently designing an FPGA-based co-processor with a general architecture as illustrated by the attached figure.

The project is built on top of Intel's PCIE Gen3 x8 DMA reference design for Arria 10 GX Development Kit. EMIF and PCIE modules are both Intel's reference IP for DDR interfacing and PCIE-based DMA operations, respectively.

The user logic (MY CORE) is a quite complex design that receives clock and reset signals from the EMIF IP (emif_usr_clk, and emif_usr_reset_n). However, the emif_usr_clk signal, which is fixed on 250 MHz, has made it almost impossible for me to meet timing constraints for my design.

I would like to know if there is a way to slow down emif_usr_clk frequency to something around 200 MHz or less. I don't want to use a different clock tree because it would force me to use cross clocking bridges between MYCORE and EMIF, adding communication and resource overhead that I can not afford right now.

Thank you in advance for any information you could share.

My best regards

Anderson