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AAmor's avatar
AAmor
Icon for New Contributor rankNew Contributor
7 years ago

How to reduce EMIF_USR_CLK frequêncy?

Hi there, folks I am currently designing an FPGA-based co-processor with a general architecture as illustrated by the attached figure. The project is built on top of Intel's PCIE Gen3 x8 DMA re...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi Sir,

The frequency of this clock is depend on the interface frequency when you configure this IP. Since you want to slow down the emif_usr_clk frequency to 200MHz, you can reduce the memory clock frequency to 800MHz. Please also note that the “Mem Timing” parameter setting might slightly change according to frequency.

And to ensure your EMIFIP configuration is within the spec, you check below EMIF spec estimator link.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support/emif.html

Hope this helps

Thanks

Regards,

NAli1