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Altera_Forum
Honored Contributor
Honored ContributorHow to realize the pipeline in mixed operation of the divider or multiplication?
If I want to calculate the following function: f = (x * y + a) / z + b; there is five input variables and they may be changed at every clock. If use combinational logic to synthsize it...
Altera_ForumHonored Contributor
Honored ContributorAs for your first question: yes it is possible for LPM_MULT and LPM_DIVIDE to yield results in one cycle... in fact, you can control the latency of the megafunctions. To do so, simply change the following lines:
lpm_mult_component.lpm_pipeline = 0, divider1.lpm_pipeline = 0, Right now, pipeline level is set to 0, meaning that it would finish computing within the same cycle. If you want to wait one more cycle, then you can simply set it to 1. Of course, there is a trade off between pipeline level and the area of the multiplier/divider. As for your second question: I suppose you can use instantiate a shift register (just 1 tap and you can specify how many cycle delay you would want from input and output... in your case 20). Otherwise, I suppose you can use a FIFO and just control when you want to read/write to/from FIFO. Hope this helps...
