How to realize the pipeline in mixed operation of the divider or multiplication?

I show you an example in the attachement.

I do y=k*(x-b) in the "Y_BOX_8" mod,as you know ,the multiplication or divider with logic element will get a low speed. so , you need a fifo with different output width befor you do multiply. For example ,the input width of your 'x' is 16 bit ,and the frequence is 100Mhz. then you need a fifo which input width if 16bit and the output width is 16*8= 128 bit,then the read clock of this fifo shoud be 100Mhz/8 = 12.5Mhz or higher. 12.5Mhz will be sure to finish the multiply operation. the only problem is that you need 8 multiplyer.

I am poor in English , if you can't understand what i said , I am sorry. send E_mail to me ,I will try my best to explain that.

good luck