How to migrate source-synchronous GPIO to Intel PHY Lite IP?

I am trying to use AN756 to understand how to implement a 300 MHz (single data rate) source-synchronous input data interface.

I previously tried to infer ordinary GPIO for this interface, but it fails timing. My target device is a Cyclone 10 GX 10CX085.

AN756 only provides this diagram (and no accompanying text to explain what it means):

After much searching and reading online, my understanding is the following:

• The external (source-synchronous) clock must be connected to StrobeIn.
  • This clock must be routed (on the PCB) to a specific x8/x9 DQS pin on the FPGA.
  • The source-synchronous data must be routed (on the PCB) to the same DQ group as StrobeIn's DQS.
• An additional RefClock must be provided.
  • Best jitter performance is usually achievable if this is an external clock.
  • The RefClock frequency must be selected from a specific list. (Ideally it is exactly half the StrobeIn frequency).
• Both reset_n and rdata_en can be held high in this use case.

Therefore, if my source-synchronous clock and data are named Clk_In and Data_In, then I think I can basically convert these to Clk_Core and Data_Core like this (in VHDL):

    i_phylite : component phylite
    port map (
        ref_clk              => Clk_Ref,
        reset_n              => '1',
        interface_locked     => open,
        core_clk_out         => Clk_Core,
        group_0_data_to_core => Data_Core,
        group_0_rdata_en     => (others => '1'),
        group_0_rdata_valid  => open,
        group_0_data_in      => Data_In,
        group_0_strobe_in    => Clk_In
    );

As far as I can see, the "General" configuration is fairly straightforward:

However the "Group 0" configuration is a bit more confusing. There are 4 parts I would like help with:

1. What does "Read latency" mean in this context? (I am not reading anything from anywhere).
2. My source-synchronous data is center-aligned (it is stable around the rising edge of the source-synchronous clock). Does this mean I should set the "Capture strobe phase shift" to 180 degrees?
3. Do I need a nonzero "OCT enable size"?
4. In the "Timing Settings", can I just enter the setup and hold times specified in the datasheet of the external device (which is outputting the source-synchronous input to the FPGA)?

Apart from this, have I generally understood how to use the PHY Lite IP correctly? This requires hardware (PCB) changes, so I would like to get it right.