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Altera_Forum
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8 years ago

How to improve timing in FIR Compiler II?

Hello @all, can anyone tell me how I can improve the timing with a filter generated by the FIRII. The top failing path has a slack of -820ps. If I locate the path in the Technology Map View...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi Kippis,

There is nothing much to optimize with the generated code. Your design may consist of (18+18) x 19 structure. If this is the case, you may try to increase the coefficient bit width to 20 or reducing the bit width to 18 and confirm whether the input registers are able to pack. This can help to determine whether the problem is due to the Quartus Synthesis.

Best Regards,

Terence

(This message was posted on behalf of Intel Corporation)