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PiotrWo's avatar
PiotrWo
Icon for New Contributor rankNew Contributor
1 year ago

How to implement PCIE hard IP for Cyclone IV GX

Hi,
I am currently working with a Cyclone IV GX FPGA: EP4CGX75CF23C7. I would like to run a PCI transceiver and map the memory (on-chip memory) to the endpoint using 1 data lane. What do I need for this in quartus II 23.1 or 24.1? I see IP_Compiler for PCI Express but I cannot find any compatible instructions on how to use it.
Thanks.

Pcie

5 Replies

  • PiotrWo's avatar
    PiotrWo
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi,

    Thanks for your help. I need some time to review the document, I hope it will help me solve the problem.

    All the best

    P.

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi FVM,


    Thanks for your help in the community question.


    Hi PiotrWo,


    I believe your queries about unable to find instruction to use IP compiler had been address by our community expert.

    Is there anything else you think we could help you ?


    Regards,

    Wincent_Altera


    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      1 year ago

      Hi PiotrWo,

      If you have further question, please file a new thread.
      Altera and the FPGA community will be full commitment to support you.

      Regards,

      Wincent_Altera

  • Tinker_Tim's avatar
    Tinker_Tim
    Icon for New Contributor rankNew Contributor
    10 months ago

    I believe the last version of Quartus II that supports PCIe Hard IP on the Cyclone 4-GX family is V18.1.
    I couldn't get later versions to find the IP or allow the Compiler to work.
    Hope this helps.

    Tink!