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I need a
bus functional model instead.
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Generally its just called an SDRAM model. A BFM is the term used for the simulation of the Avalon-MM master/slave and the AXI interfaces.
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If you already knew about all of that then the big question is why wasn't that the focus instead of trying to do it manually?
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Did you not read Post# 43?
What you describe works perfectly well for DDR, but it appears that it does not work for SDRAM. Basically Altera did not add that feature for SDRAM.
You could always file a Service Request and ask them how they expect you to simulate their SDRAM Controller. Perhaps they'll have a recommendation.
Either way, the method I have told you to create a testbench with an SDRAM model works perfectly fine. The hard part seems to be finding a VHDL/Verilog model!
Cheers,
Dave
Honored Contributor
