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I see that a test bench was either created by hand
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Pretty much all testbenches are created by hand, since your tests are project specific :)
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I have a 42s16400j_t.ibs file and an existing test bench
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What is an .ibs file? Sounds like an IBIS file to me, and you would not use that as an SDRAM model. Are you sure you've downloaded something that is actually useful???
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handful of steps
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1. Create Qsys system
2. Instantiate Qsys system in your top-level design (assuming the Qsys is not your top-level design)
3. Instantiate your top-level design in your testbench
4. Instantiate the SDRAM model in your testbench
5. Run your simulation
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It shouldn't involve writing the simulation for the entire SDRAM initialization process or anything like that
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Why? You need to check that the SDRAM is initialized correctly. Most SDRAM models have a faster initialization sequence in simulation.
Cheers,
Dave
Honored Contributor
