How to implement DE0 SDRAM as 2-port RAM

I ran the tcl script in modelsim, saw the waveform, and understand what is being shown. I looked through the vhd files also included. I see that a test bench was either created by hand or generated. That doesn't really answer my immediate questions though.

I have a 42s16400j_t.ibs file and an existing test bench. I'm looking for the specific, handful of steps that integrate this simulation model file with modelsim, and then the small corrections that need to be made to the SDRAM instance in my existing test bench (which was generated by QSYS and then modified by me). It shouldn't involve writing the simulation for the entire SDRAM initialization process or anything like that. Wouldn't there be a few steps involved in importing the 42s16400j_t.ibs file to modelsim, followed by the slight modification of my existing test bench? The warning output in modelsim that I posted earlier seems to imply that..