How to implement DE0 SDRAM as 2-port RAM

I have modelsim 10.1c SE installed and a testbench made but I need a SDRAM simulation model. Any idea what the detailed steps are to get one set up in modelsim?

# This reference design requires a vendor simulation model.
#  To simulate accesses to SDRAM, you must:
#        - Download the vendor model
#        - Install the model in the system_sim directory
#        - Add the vendor file to the list of files passed to 'vcom' in setup_sim.do
#        - Instantiate sdram simulation models and wire them to testbench signals
#        - Be aware that you may have to disable some timing checks in the vendor model
#               (because this simulation is zero-delay based)