Honored Contributor
Honored ContributorI see. I can't really run simulations currently because of modelsim's sinlge-HDL restriction. I'll have to find a way around that..
There is an upside of lower cost if SDRAM ends up working out though. These will replace our current products if I ever get that far with it. Getting a clean 640x480 image is only step one in a 30+ step development process. As of writing this, the entire system is QSYS-based. The image has lost all of its noise but now has an interlaced-look to it (see attached image). QSYS did automatically create a FIFO, among other things, automatically which was nice. I now have to take wild guesses as to what is causing that interlaced look.. The camera and VGA entity ended up as "Bridges and Adapters/Streaming" modules which have Avalon Memory Mapped Master interfaces. One category of settings which is very likely to be wrong are the ones in the attached image. Do any of those stand out as definitely wrong to you? I don't know what "bits per symbol" is in this context. I'll have to look into that... UPDATE: It has a combination of pixelation, as if a 20x20 square is treated as one block, and an interlaced effect which gets worse as I slow the clock down from a starting point of 166MHz
