Honored Contributor
Honored ContributorI'll read up on arbitration.
What's going on is the camera entity has it's own clock and is just churning out address + data values that represent the pixel locations and pixel colors that it sees. It can't wait, or buffer, or anything. I'll probably have to use a FIFO memory component that uses the FPGA's limited memory. The vga_out entity is doing the same thing at it's own independent clock rate except that it is asking for pixel data for a given address location. Both entities read and write to the same address space for now. They also often request SDRAM access at the same time. I can't just have it wait until a complete frame is written to memory because that will interfere with the display image. What I really need is the closest thing possible to a 2-port RAM.
