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There are no packets or other data that can be reliably grouped or streamed.
There are two different entities requesting to read and write from unpredictable addresses at unpredictable times usually simultaneously.
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But you call them camera and VGA interfaces. I would have thought they would work on frames of data.
Based on your comments, the interfaces would not be implemented as Avalon-ST streams, but they do sound like they can be implemented as Avalon-MM master interfaces.
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So far I've created the QSYS component for the camera. I think I picked bridges and adapters/Avalon ST. It ended up being a memory master though after I set all of the parameters.. I messed up and made all the exports reside under one conduit name but other than that it
might work.. I have a feeling I can't just connect the two masters to the SDRAM controller and trust that it will just 'figure' it out.
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Yes, you can. So long as the two masters implement the Avalon-MM protocol correctly, then read and writes should work fine. You would use your simulation to determine if the default arbitration shares are appropriate, or whether you need to change them.
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There is probably some component that needs to handle that.. It would set priority like you mentioned earlier.. Any idea what component that would be?
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Stop making me repeat myself. If you're not going to read the documentation on Qsys, arbitration, and arbitration shares, then I'll just stop responding to this thread.
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Maybe a frame buffer? I hope not because I want to be able to store and retrieve all sorts of other data using this SDRAM chip and random times..
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This is what you need a simulation to determine. If data read pre-fetching or write-posting is appropriate in your design, then a buffer between your devices and the SDRAM might be sufficient. This buffering would be most efficient if your data transfers occur in blocks, but you make it sound like that is not the case.
Cheers,
Dave
Honored Contributor
