How to implement DE0 SDRAM as 2-port RAM

I've condensed the camera and vga entities so that there is a single, top level file for both.

When creating a new component in QSYS, I'm having trouble guessing which group needs to be selected.

Any of the following seem like they could be right:

Bridges and Adapters/Memory-Mapped,

Bridges and Adapters/DMA,

Bridges and Adapters/Streaming,

Bridges/Memory-Mapped,

Bridges/Streaming,

or Qsys Interconnect/Memory-Mapped

The camera basically outputs address, data, and write enable while the vga entity basically outputs an address and accepts pixel data.

Which "group" best fits these two entities?

Inst_ov7670_controller : entity work.ov7670_top PORT MAP(
			clk             => clk_camera,
			resend          => "not"(btn(2)),
			config_finished => led(9),  -- out
			sioc            => ov7670_sioc, -- out
			siod            => ov7670_siod, -- inout
			reset           => ov7670_reset,
			pwdn            => ov7670_pwdn,
			xclk            => ov7670_xclk,
			pclk            => ov7670_pclk,
			rez_160x120     => rez_160x120,
			rez_320x240     => rez_320x240,
			vsync           => ov7670_vsync,
			href            => ov7670_href,
			d               => ov7670_data,
			addr            => wraddress(18 downto 0),	-- WRITE ADDRESS OUT -->
			dout            => wrdata(11 downto 0), 	-- WRITE DATA OUT -->
			we              => wren     				-- WRITE ENABLE OUT -->
		);
	Inst_VGA_controller : entity work.vga_top PORT MAP(
			CLK25       => clk_vga,
			rez_160x120 => rez_160x120,
			rez_320x240 => rez_320x240,
			Hsync       => hsync,       --out
			Vsync       => vsync,       --out
			
			Din         => rddata(11 downto 0), -- <-- READ DATA INPUT
			R           => vga_r,
			G           => vga_g,
			B           => vga_b,
			
			address     => rdaddress(18 downto 0) -- READ ADDRESS OUT -->
		);