Honored Contributor
Honored Contributormultiple avalon-mm masters
--- Quote Start --- When you say create two Avalon-MM master interfaces, are you implying that (A) the camera entity and vga entity be modified to conform to Avalon-MM master standards like you were saying earlier, or ( B ) to use some sort of generic Avalon-MM master interface component and export the signals for use in the original top_level file? If it is A, it will take a while to find some sort of documentation or example. If it is B, what is the specific IP component name? --- Quote End --- Both A and B are identical. The only difference is that you've moved the master interface logic out of the Qsys system. What you need is a way to get your camera and VGA interfaces into Qsys. I would have thought these devices were already supported by the Altera Video and Image Processing tools, though I have never needed to use them. Did you look at their IP cores? You need to simulate single master access to SDRAM using a BFM, and then once you have that working, add a second BFM. Then generate simultaneous reads and write to see what happens. Then go into Qsys and change the priorities used by the multi-master arbitration logic, and repeat your simulation. Only then will you understand how the SDRAM can be shared. This tutorial shows how to use the Verification IP ... http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial and this thread has an updated zip file with an Avalon-MM BFM master and slave example (see Post# 25) http://www.alteraforum.com/forum/showthread.php?t=32952&page=3 Cheers, Dave
