How to implement DE0 SDRAM as 2-port RAM

pll phase-control

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For example, the Altera ALTPLL has dynamic phase adjust options. I enabled that and all of the new ports such as phasecounterselect[], phasestep, and phaseupdown made sense except for scanclk. So I looked at the IP user guide for that and it just says that it's the input clock for the serial scan chain. That doesn't tell me whether I should set it to '1', '0', or feed a clock into it. I mapped phasecounterselect[] to switches, phasestep and phaseupdown to buttons, and hooked up an oscilloscope to try to see the phase shift in real-time but I couldn't gt the phase to change no matter what I did with scanclk port.

I also wanted to know why the ALTPLL has seemingly unnecessary avalon slave ports such as altpll_0_pll_slave_read, altpll_0_pll_slave_write, altpll_0_pll_slave_address, altpll_0_pll_slave_readdata, and altpll_0_pll_slave_writedata. My best guess as to what to do with these is just to set them all to '0' and open. The Altera ALTPLL user guide didn't really answer that question either..

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The ALTPLL and ALTPLL_RECONFIG describe how reconfiguration and the scan chain work. I implemented a scan chain controller in this thread;

http://www.alteraforum.com/forum/showthread.php?t=46527

The Qsys ports you mention could be an Avalon-MM master interface for reading .MIF memory files from external slave RAM.

It does not sound like you really need to be able to control the PLL phase-shift. If you perform a TimeQuest timing analysis, and your SDRAM passes timing, it should be fine.

Cheers,

Dave