How to implement DE0 SDRAM as 2-port RAM

sdram timing analysis

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If 133.33Mhz is the maximum frequency at which they guarantee it meets timing spec then what are the other operating frequencies of 143MHz, 166MHz, and 200MHz for? I interpreted to mean that the SDRAM chip can operate at either 133MHz, 143MHz, 166MHz, or 200MHz. I don't doubt that you're right, I just want to understand why because the information is conflicting. Here is the spec sheet: http://www.issi.com/ww/pdf/42-45s16400j.pdf

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The "KEY TIMING PARAMETERS" table has the relevant details. It says speed grade -5 when operated at a CAS latency of 3 has a minimum guaranteed operating frequency of 200MHz, but when you operate it with a CAS latency of 2 the minimum guaranteed operating frequency is 133MHz. You can interpret the other columns similarly. If you look at the package marking on the ISSI RAM on your board, you'll likely find that it has a -7 speed grade marking.

The SDRAM controller Qsys component has a page where you enter timing parameters. In the example I wrote for the DE0-nano SDRAM,

Run the DE0-nano example, open Qsys, double-click on the SDRAM controller, click next to get to the timing page, and you'll see the CAS latency set to 3. I'm pretty sure I modified the power-up delay and the refresh command time from the default values based on the data sheet, and perhaps a few of the other parameter too. Basically I changed the values that were obvious, then synthesized the design, and since everything worked, I moved on :)

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I have noticed that in every QSYS example that uses SDRAM, both from Altera, and from 3rd parties, the clock used for the SDRAM controller and the SDRAM_CLK output is only 50Mhz. There is also always a -3ns phase shift applied but it isn't clear whether this phase-shifted clock signal should go to (A) the SDRAM controller and the SDRAM_CLK output, ( B ) just the SDRAM controller while a regular 50MHz clock goes to the SDRAM_CLK output, or (C) just the SDRAM_CLK output while a regular 50MHz clock goes to the SDRAM controller. Is it A, B or C in your opinion?

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My opinion is encoded in the DE0-nano example :)

Run the DE0-nano example. Select Tools->TimeQuest timing analyzer.

1. FPGA SDRAM interface input setup timing

a) Click on Report Timing

b) In the Report Timing GUI enter

Targets From: [get_keepers {sdram_dq[*]}]

Report panel name: Setup Timing

Click on Report Timing

2. FPGA SDRAM interface input hold timing

a) Click on Report Timing again

b) In the Report Timing GUI enter

Targets From: [get_keepers {sdram_dq[*]}]

Analysis type: Hold

Report panel name: Hold Timing

Click on Report Timing

3. FPGA SDRAM interface clock-to-output max (SDRAM input setup) timing

a) Click on Report Timing

b) In the Report Timing GUI enter

Targets To: [get_keepers {sdram_dq[*]}]

Report panel name: Tco(max) Timing

Click on Report Timing

4. FPGA SDRAM interface clock-to-output min (SDRAM input hold) timing

a) Click on Report Timing again

b) In the Report Timing GUI enter

Targets To: [get_keepers {sdram_dq[*]}]

Analysis type: Hold

Report panel name: Tco(min) Timing

Click on Report Timing

Now, look at all the timing diagrams by selecting each of the timing reports.

5. Go back to the DE0-nano design and open the PLL in the MegaWizard or IP Catalog, and change the PLL phase-shift of the second output clock to zero.

I double-clicked on the PLL in the hierarchy display and then clicked next until I got to the c1 output, and edited the -90 degree PLL phase shift to be 0. Click next and then Finish to update the PLL instance.

6. Re-run synthesis by pressing the Play button in the GUI. TimeQuest will show errors.

7. Re-run the TimeQuest analysis steps above.

Repeat step 5 for various phase-shifts. Read the comments in the timing constraints file de0_nano.sdc file.

Each design will have an ideal phase-shift for the SDRAM. You can determine whether or not your analysis is correct by replacing the PLL with one that has a programmable phase-shift, and then sweep the PLL phase and test whether reads and writes to SDRAM work. The External Memory Interface toolkit does this for DDR interfaces.

Cheers,

Dave