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If the SDRAM chip operates at a minimum of 133MHz
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For SDRAM, that is a minimum guaranteed operating frequency, i.e., its really the maximum frequency at which they guarantee it meets timing spec (yes, its confusing!).
DDR SDRAM uses a PLL. Their data sheets do have a minimum frequency specification for when the PLL can be used.
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What I think is happening is there are instances where the ram needs to be read at the same time that pixel data needs to be written. Regardless of the fact that the ram clock is 4x faster than the pixel and vga clocks, there are still going to be instances where they request ram usage at the same time. What is the standard way of handling this type of conflict?
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I've already told you; multi-master arbitration.
You can create a Qsys system with two Avalon-MM master interfaces connected to the SDRAM controller, and the Qsys fabric that connects the two masters to the SDRAM slave will include arbitration logic. You can set the arbitration shares to determine whether one master gets higher priority over another, you can add pipelining-bridges and other bells-and-whistles if you want data to be pre-fetched or buffered.
All of this requires you read and understand the Avalon Specification, the Verification IP Guide (for BFMs), and the users guides associated with the IP you add to your system.
I've pointed you in the right direction, hopefully you'll invest some time to read these documents. As I have said before, simulation of your design will answer most of the questions you have regarding the IP.
Regarding using TimeQuest. Rsync has a few nice tutorials on the AlteraWiki. Read those.
Cheers,
Dave
Honored Contributor
