Honored Contributor
Honored ContributorI began writing the simulation but when I wen to test it in modelsim, modelsim reported that it only supports one HDL. Since some of the files are verilog (generated by QSYS) it won't allow simulation.
I did get the SDRAM working but the display is mostly noise. I can tell it is somewhat working because the general color of the noise changes predictably as I aim the camera from a dark area to a bright area. The noise is likely because of issues with two masters fighting for access to the SDRAM chip. Also the sdram_controller_s1_waitrequest signal seems to be always high. 1. Is there possibly a required init period that I'm not allowing time for? 2. Is there a better way to delegate access to the SDRAM chip than what I'm doing below? Maybe alternate every other clock cycle? The SDRAM chip is made by ISSI. The pdf for this specific chip states that the acceptable clock frequencies are 133, 143, 166, & 200MHz. The altera tutorials that involve sdram instruct you to create a ALTPLL with a 50mhz output and a -3ns phase shift for the SDRAM. I was using a 100Mhz PLL with a -3ns phase shift. I'll try other frequencies. 3. Do you know what frequency I should be using? The information seems to be conflicting. sdram_controller : process(sdram_clk_s, btn(2))
begin
if btn(2) = '0' then
sdram_controller_s1_address_s <= (others => '0');
elsif rising_edge(sdram_clk_s) then
if (wren = '0') then
sdram_controller_s1_address_s <= rdaddress;
else
sdram_controller_s1_address_s <= wraddress;
end if;
end if;
end process;
SDRAM_BA_1 <= sdram_controller_wire_ba_s(1);
SDRAM_BA_0 <= sdram_controller_wire_ba_s(0);
SDRAM_UDQM <= sdram_controller_wire_dqm_s(1);
SDRAM_LDQM <= sdram_controller_wire_dqm_s(0);
SDRAM_ADDR <= '0' & sdram_controller_wire_addr_s(11 downto 0);
SDRAM_CLK <= sdram_clk_s;
wraddress(21 downto 19) <= (others => '0');
rdaddress(21 downto 19) <= (others => '0');
wrdata(15 downto 12) <= (others => '0');
Inst_sdram : entity work.SDRAM_QSYS port map(
clk_100mhz_clk => sdram_clk_s, --: in std_logic := '0'; clk.clk
reset_reset_n => btn(2), --: in std_logic := '0'; reset.reset_n
sdram_controller_wire_addr => sdram_controller_wire_addr_s, --: out std_logic_vector(11 downto 0); sdram_controller_wire.addr
sdram_controller_wire_ba => sdram_controller_wire_ba_s, --: out std_logic_vector(1 downto 0); .ba
sdram_controller_wire_cas_n => SDRAM_CAS_N, --: out std_logic; .cas_n
sdram_controller_wire_cke => SDRAM_CKE, --: out std_logic; .cke
sdram_controller_wire_cs_n => SDRAM_CS_N, --: out std_logic; .cs_n
sdram_controller_wire_dq => SDRAM_DQ, --: inout std_logic_vector(15 downto 0) := (others => '0'); .dq
sdram_controller_wire_dqm => sdram_controller_wire_dqm_s, --: out std_logic_vector(1 downto 0); .dqm
sdram_controller_wire_ras_n => SDRAM_RAS_N, --: out std_logic; .ras_n
sdram_controller_wire_we_n => SDRAM_WE_N, --: out std_logic; .we_n
sdram_controller_s1_address => sdram_controller_s1_address_s, --: in std_logic_vector(21 downto 0) := (others => '0'); sdram_controller_s1.address
sdram_controller_s1_byteenable_n => "11", --: in std_logic_vector(1 downto 0) := (others => '0'); .byteenable_n
sdram_controller_s1_chipselect => '1', --: in std_logic := '0'; .chipselect
sdram_controller_s1_writedata => wrdata, --: in std_logic_vector(15 downto 0) := (others => '0'); .writedata
sdram_controller_s1_read_n => wren, --: in std_logic := '0'; .read_n
sdram_controller_s1_write_n => "not"(wren), --: in std_logic := '0'; .write_n
sdram_controller_s1_readdata => rddata, --: out std_logic_vector(15 downto 0); .readdata
sdram_controller_s1_readdatavalid => led(5), --: out std_logic; .readdatavalid
sdram_controller_s1_waitrequest => led(4) --: out std_logic
);
