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1. In the DE0 manual, the size of SDRAM_ADDR is 13bits, [12:0], but the wizard generates a 12 bit vector, [11:0]. Which one is right if the SDRAM size is 8Mb?
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Check the data sheet for the SDRAM. Most board designers are conservative and include "extra" address bits to make the board suitable for loading several device sizes.
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2. Do you see anything wrong with the "sdram_controller_wire" block of signals? Like BA or DQM are backwards?
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What do you mean by backwards? The port direction appears correct - the controller drives those signals.
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sdram_controller_s1:
3. Is chip select just used to enable sdram_controller_s1?
4. What is byte enable for in this instance?
5. Why isn't read_n and write_n one signal instead of two? Does that mean you can write and read at the same time?
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Create a simulation model and use that to answer these questions :)
Its likely that chipselect and read_n need to assert for read, and chipselect and write_n need to assert for write.
Cheers,
Dave
Honored Contributor
