How to implement DE0 SDRAM as 2-port RAM

Seems like I'm making progress.. I have a few questions about entity instance below:

sdram_controller_wire:

1. In the DE0 manual, the size of SDRAM_ADDR is 13bits, [12:0], but the wizard generates a 12 bit vector, [11:0]. Which one is right if the SDRAM size is 8Mb?

2. Do you see anything wrong with the "sdram_controller_wire" block of signals? Like BA or DQM are backwards?

sdram_controller_s1:

3. Is chip select just used to enable sdram_controller_s1?

4. What is byte enable for in this instance?

5. Why isn't read_n and write_n one signal instead of two? Does that mean you can write and read at the same time?

     -- sdram controller
    sdram_controller : process(clk50, btn(2))
    begin
        if btn(2) = '0' then
            sdram_controller_s1_address_s <= (others => '0');
        elsif rising_edge(clk50) then
            if (wren = '0') then
                sdram_controller_s1_address_s <= wraddress;
            else
                sdram_controller_s1_address_s <= rdaddress;
            end if;
        end if;
    end process;
    SDRAM_BA_1 <= sdram_controller_wire_ba_s(1);
    SDRAM_BA_0 <= sdram_controller_wire_ba_s(0);
    SDRAM_UDQM <= sdram_controller_wire_dqm_s(1);
    SDRAM_LDQM <= sdram_controller_wire_dqm_s(0);
    SDRAM_ADDR <= '0' & sdram_controller_wire_addr_s(11 downto 0);
    Inst_sdram : entity work.SDRAM_QSYS port map(
            clk_100mhz_clk                    => sdram_clk_s, --: in    std_logic                     := '0';                                       clk.clk
            reset_reset_n                     => btn(2), --: in    std_logic                     := '0';                                     reset.reset_n
            sdram_controller_wire_addr        => sdram_controller_wire_addr_s, --: out   std_logic_vector(11 downto 0);                            sdram_controller_wire.addr
            sdram_controller_wire_ba          => sdram_controller_wire_ba_s, --: out   std_logic_vector(1 downto 0);                                                  .ba
            sdram_controller_wire_cas_n       => SDRAM_CAS_N, --: out   std_logic;                                                                     .cas_n
            sdram_controller_wire_cke         => SDRAM_CKE, --: out   std_logic;                                                                     .cke
            sdram_controller_wire_cs_n        => SDRAM_CS_N, --: out   std_logic;                                                                     .cs_n
            sdram_controller_wire_dq          => SDRAM_DQ, --: inout std_logic_vector(15 downto 0) := (others => '0');                              .dq
            sdram_controller_wire_dqm         => sdram_controller_wire_dqm_s, --: out   std_logic_vector(1 downto 0);                                                  .dqm
            sdram_controller_wire_ras_n       => SDRAM_RAS_N, --: out   std_logic;                                                                     .ras_n
            sdram_controller_wire_we_n        => SDRAM_WE_N, --: out   std_logic;                                                                     .we_n
            sdram_controller_s1_address       => sdram_controller_s1_address_s, --: in    std_logic_vector(21 downto 0) := (others => '0');           sdram_controller_s1.address
            sdram_controller_s1_byteenable_n  => "11", --: in    std_logic_vector(1 downto 0)  := (others => '0');                              .byteenable_n
            sdram_controller_s1_chipselect    => '1', --: in    std_logic                     := '0';                                          .chipselect
            sdram_controller_s1_writedata     => wrdata, --: in    std_logic_vector(15 downto 0) := (others => '0');                              .writedata
            sdram_controller_s1_read_n        => wren, --: in    std_logic                     := '0';                                          .read_n
            sdram_controller_s1_write_n       => not wren, --: in    std_logic                     := '0';                                          .write_n
            sdram_controller_s1_readdata      => open, --: out   std_logic_vector(15 downto 0);                                                 .readdata
            sdram_controller_s1_readdatavalid => open, --: out   std_logic;                                                                     .readdatavalid
            sdram_controller_s1_waitrequest   => open --: out   std_logic      
        );