Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

How to implement DE0 SDRAM as 2-port RAM

I currently use the tiny bit of memory on the FPGA for a computer vision project but it's way too limited. I have a stand-alone SDRAM controller from Altera (partially pasted below) but I need one mo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I'm having an issue where I want to use one of the FIFO, frame buffer, or 1-port ram IP cores but since I'm not using a NioII, I just have to export everything and end up with even more connections to map. I'm trying to get back to the same position I was in with the on-board FPGA memory where all I have map is a rd_clk, rd_addr, rd_data, wr_clk, wr_addr, and wr_data. (Of course the SDRAM pins will also be mapped to the device.) Is there a way to get what I described?