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It looks like it will work but I'm still messing with it...
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I haven't tried this with the SDRAM controller, but with the DDR controller, you can have Qsys generate a testbench, and it will include an DDR SDRAM model.
For DDR SDRAM, I get Qsys to generate a top-level testbench, and then use that as a template for my own testbench. The piece of code I am typically interested in, is the SDRAM model instance, i.e., the fake SDRAM that the SDRAM controller reads/writes to. I then go back to the Qsys system and add a BFM, or I'd connect to the Avalon-MM slave port you're going to export to your top-level design, and use that to generate Avalon-MM transactions.
Cheers,
Dave
Honored Contributor
