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It seems like QSYS is for projects where the developer wants to use a NiosII processor or JTAG interface.
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No, Qsys is for projects where you want to connect Avalon-MM devices together without having to "think" about how all the glue logic is generated.
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I want to focus on making the wrapper for the SDRAM controller. It is likely only an hour or less of work for someone more experienced than myself. What is the next step in getting assistance in developing this wrapper?
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Follow along, and lets see if we can get you an SDRAM wrapper ...
1. Download the DE0-nano SDRAM example design
http://www.alteraforum.com/forum/showthread.php?t=45927 This gives us a starting point. Ignore the fact that the DE0 may have different SDRAM.
2. Unzip it and build it per the readme.txt instructions, i.e.,
Quartus Tcl:
tcl> cd {
c:\temp\de0_nano_sdram} tcl> source scripts/synth.tcl
The build procedure creates the qsys_system.qsys file and "Generates" the Qsys system files.
WRAPPER GENERATION METHOD# 1
3. Look at the generated source
c:\temp\de0_nano_sdram\qsys_system\synthesis\submodules\qsys_system_sdram.v There's your wrapper code right there. Its got an Avalon-MM slave interface and the SDRAM interface.
WRAPPER GENERATION METHOD# 2
4. Delete the generated source, i.e., delete the folder
c:\temp\de0_nano_sdram\qsys_system\synthesis 5. Start Qsys, open qsys_system.qsys
6. Delete the clock and JTAG master, leaving only the SDRAM component.
7. "Export" all of the SDRAM ports, eg., sdram_clk, sdram_reset, sdram_slave, sdram_mem.
8. Look at the HDL Example - its pretty much identical to the wrapper code (with port name changes)
9. Try to "Generate" this new system and ... failure ... at least on 12.1sp1 as there is no clock defined, which the SDRAM generator must need.
A slight variation on this is to export an Avalon-MM master from the Qsys system. Your external logic would then control that master interface. Why is this a better option? It allows you to let Qsys generate the SDRAM controller.
Note that an SDRAM controller is not that difficult to write. Its only a state machine and logic. There are probably examples on the OpenCore web site. Its much harder to write a DDR SDRAM controller, so that is one case where you'd definitely want to re-use the Qsys generated DDR controller. In the case of an SDRAM controller, you might want to find a non-Qsys version (Altera used to have an example design, long before the days of Qsys).
Cheers,
Dave
Honored Contributor
