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Altera_Forum
Honored Contributor
Honored ContributorHow to implement DDR LVDS on Stratix IV?
What's the best way to implement simple 2:1 serialization for LVDS interface on Stratix IV? Using a DDR megafunction? Or ALTLVDS with deserializaiton factor of 2? When selecting deserialization factor of two, the DPA is bypassed and I can't get Quartus to place any of the pins. It doesn't use a PLL in this case, but does require some grouping assignments (thinks it's a memory interface). What's the simplest method?
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Altera_ForumWhat speed are you running?
How wide is the interface? Do you need the DPA? Did you try it with the altddio (DDR)? Jake- Altera_Forum
I think, an altddio Megafunction respectively a direct instantiation of altddio_out and altddio_in is the most simple way. It's also the building block for software LVDS functions with wordlengths, that are unsupported by the LVDS Megafunction.
