How to generate tx_clk for TSE

In my design, there are four TSE core. I used a PLL generate two clock, tx_clk_125m and tx_clk_25m. And four altclkctrl to select tx_clk from these two clock for each TSE. But on the fitter process, Quartus report an error.

If i use only one altclkctrl to select one tx_clk for all TSE, thers is no error.

The same PLL out can't connect to more than one altclkctrl? If like that, whether i need four PLL?:confused: