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Altera_Forum's avatar
Altera_Forum
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16 years ago

How to generate a design in verilog with DSP Builder and Simulink

Hi all,

I use Matlab->SIMULINK to design a system (with DSP Builder). I generate the .vhdl but I don't know how to make the .v . I don't find the option to generate the .v.

Someone does have an idea please ?

Best regards,

Jeremy.:confused:

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    DSP Builder only generates VHDL files. There is now way to generate verilog files I'm afraid.