how to ENABLE/DISABLE parts of an IP-core depending on the instance parameters??

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@Dave: Fortunately I have not to simulate the IP-Cores. As I interpret your recommendation, you are using a tcl-file to describe your top-level instance, right? And the top-level consists of several filesets containing VHDL-designs and simulation information. Again these filesets will be modified in the fileset_callback procedure according to the users choice.

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Not quite. I use the Tcl file to *create* the top-level instance.

-- avs_single_port_ram_template.vhd
--
library ieee;
use ieee.std_logic_1164.all;
entity avs_single_port_ram_template is
    port (
        -- Reset and clock
        clk         : in  std_logic;
        rstN        : in  std_logic;
        -- Avalon Slave Interface
        avs_read    : in  std_logic;
        avs_write   : in  std_logic;
        avs_addr    : in  std_logic_vector(ADDR_WIDTH_MINUS_1_VAL downto 0);
        avs_byteen  : in  std_logic_vector(BYTEEN_WIDTH_MINUS_1_VAL downto 0);
        avs_wrdata  : in  std_logic_vector(DATA_WIDTH_MINUS_1_VAL downto 0);
        avs_rddata  : out std_logic_vector(DATA_WIDTH_MINUS_1_VAL downto 0);
        avs_rdvalid : out std_logic;
        avs_wait    : out std_logic
    );
end entity;
architecture avs_wrapper of avs_single_port_ram_template is
    component avs_single_port_ram is
        generic (
            ADDR_WIDTH   : integer;
            BYTEEN_WIDTH : integer;
            DATA_WIDTH   : integer
        );
        port (
            clk         : in  std_logic;
            rstN        : in  std_logic;
            avs_read    : in  std_logic;
            avs_write   : in  std_logic;
            avs_addr    : in  std_logic_vector(  ADDR_WIDTH-1 downto 0);
            avs_byteen  : in  std_logic_vector(BYTEEN_WIDTH-1 downto 0);
            avs_wrdata  : in  std_logic_vector(  DATA_WIDTH-1 downto 0);
            avs_rddata  : out std_logic_vector(  DATA_WIDTH-1 downto 0);
            avs_rdvalid : out std_logic;
            avs_wait    : out std_logic
        );
    end component;
begin
    u1: component avs_single_port_ram
        generic map (
            ADDR_WIDTH   => ADDR_WIDTH_VAL,
            BYTEEN_WIDTH => BYTEEN_WIDTH_VAL,
            DATA_WIDTH   => DATA_WIDTH_VAL
        )
        port map (
            clk         => clk,
            rstN        => rstN,
            avs_read    => avs_read,
            avs_write   => avs_write,
            avs_addr    => avs_addr,
            avs_byteen  => avs_byteen,
            avs_wrdata  => avs_wrdata,
            avs_rddata  => avs_rddata,
            avs_rdvalid => avs_rdvalid,
            avs_wait    => avs_wait
        );
end architecture;

and the Tcl file "fills in the details" using the generate call-back

#  -----------------------------------------------------------------#  Generation#  -----------------------------------------------------------------# 
proc generate {} {
    send_message info "Starting generation of the RAM"
    
   #  Output file location and instance name
    set outlang  
    set outdir   
    set outname  
    if { == 0} {
        send_message info "language = $outlang, file = $outdir/$outname.vhd"
    } else {
        send_message warning "This component will be generated using VHDL."
    }
        
   #  Get the parameter values;
   #    These parameters require the following settings above:
   #     - AFFECTS_GENERATION true
   #        This setting enables the calls to get_parameter_value
   #     - HDL_PARAMETER false
   #        This parameter suppresses a check for these generics
   #        in the top-level generated file. Those generics are
   #        hidden inside the top-level instance.
   # 
    set params {
        BYTEEN_WIDTH
        ADDR_WIDTH
        DATA_WIDTH}
    foreach param $params {
       #  Get the parameters from SOPC Builder
        set $param 
       #  Print the parameters to the generate console                
        eval send_message info \"$param = $$param\"
    }
    
   #  Create the 'minus 1' versions
    set BYTEEN_WIDTH_MINUS_1 
    set ADDR_WIDTH_MINUS_1   
    set DATA_WIDTH_MINUS_1   
   #  Instance file generation
   # 
   #   - read in the template file
   #   - use Tcl string replacement to create an instance
   #     version of the template
   #   - write out the template file
   # 
    
   #  Open the template file
    set file "avs_single_port_ram_hw_template.txt"    
    if {} {
        send_message error "open $file failed"
    }
    
   #  Read the template into a buffer
    set buffer 
    close $fd
   #  Replace the entity and architecture strings
    set buffer  $buffer]
    
   #  Replace the generic values (suffixed by _VAL in the template)
    set params {
        BYTEEN_WIDTH
        ADDR_WIDTH
        DATA_WIDTH
        BYTEEN_WIDTH_MINUS_1
        ADDR_WIDTH_MINUS_1
        DATA_WIDTH_MINUS_1}
    foreach param $params {    
        eval set buffer \ \$buffer\]
    }
    
   #  Write the instance file
    set file "$outdir/$outname.vhd"
    if {} {
        send_message error "open $file failed"
    }
    puts $fd $buffer
    close $fd
   #  Add the generated file to the project
    add_file "$outdir/$outname.vhd" {SYNTHESIS SIMULATION}
}

I've uploaded the code. I just pulled this out of my code tree, it should work, but if I've missed a file, let me know and I'll upload a working example.

Cheers,

Dave