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Honored Contributor
Honored Contributorhow to efficiently drive async SRAM?
What's a good way to use async SRAM? I'm working on a Nios II system for a legacy hardware (Cyclone II) which has fast external asychronous SRAM. In fact two IS61LV51216 chips (512k*16, 8ns) in...
Altera_ForumHonored Contributor
Honored ContributorI'm surprised that you need a setup time for the write operation. Setting setup and hold to 0 and individual read and write wait states should work IIRC.
The Avalon tristated bus doesn't support bursts. You can try and support pipelined transfers instead, which should have the same performance with an SRAM.
