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Altera_Forum
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15 years ago

how to design a low pass digital filter with smallest delay

Hello, All I want to design a digital filter with the cutoff frequency 20Hz. The sampling frequency of my acquiring system is very high, up to 8192 Hz. The important requirement is the de...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I don't quite get the given figures.

For a linear FIR, group delay = order/2 in samples e.g. for 81 taps, delay = (81-1)/2 = 40 samples.

Each sample on 8192Hz takes 1000/8192 msec

so total delay for 81 taps filter = 5 msec.

You may also design minimal delay FIR while keeping phase near linear.