How to decode very wide and pipelined bus?

I don't know of any existing material but I recommend using a micro core based approach for this. This approach just means that you use multiple small cores that are tuned for specific tasks that are assembled to an end goal. This is commonly used in packet processing when you need to strip header/command information out of the packet in a sensible and reusable way.

In your case unless I'm missing something I could see the 32--> 512 bit deserialization being one core with a streaming output that feeds more cores downstream and perform address and command decode, which then feed what I presume would be a master if you need to pack datagrams into memory.