How to construct the full synchronous Video clock in and video clock out by VIP?

Hi Faisal,

Quote:

you cannot get output if your clocked_video_input module is directly connected with clocked_video_output. just put a scaler block between video_in and video_out block and keep the output resolution of scaler to input the resolution (scaling factor of 1).

That the system requires a scaler with a 1:1 ratio to work makes no sense. The only way that this would change your system is by affecting the signal propagation around the FPGA, and adding some latency (not buffering.) I think that you have a timing issue that you can fix with TimeQuest.

Quote:

you cannot get output if your clocked_video_input module is directly connected with clocked_video_output.

This should (has for me) work if

a) the output clock is equal to or derived from the input clock, and

b) the resolutions are the same

This will give the same frame rate. Frame rate is critical as the differences in the frame ultimately determine your buffering requirements and the under/over flow performance in your system.