How to constraint clocks from the ASI IP Core?

I'm using the ASI core in a Cyclone III, try something like this:

derive_pll_clocks -create_base_clocks

set rx_clk135 "ASI_RX_PLL_1|altpll_component|auto_generated|pll1|clk[0]"

set rx_serial_clk "ASI_RX_PLL_1|altpll_component|auto_generated|pll1|clk[1]"

set rx_serial_clk_90 "ASI_RX_PLL_1|altpll_component|auto_generated|pll1|clk[2]"

set_max_delay -from $rx_serial_clk -to $rx_clk135 4.430;

set_min_delay -from $rx_serial_clk -to $rx_clk135 0.000;

# added this to make sure the sample_a/b/c/d registers were not located in the wrong place. :-)

set_max_delay -from ASI_RX_Pi

[*] -to * 4.50;

Don't forget to add the location constraints for the sample_a, sample_b, sample_c, and sample_d registers too.