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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to constrain tse on cyclone III board

Hi all, I have a cyclone III board with Marvell 88E1111 RGMII PHY. I am trying to send packet from host to FPGA using RGMII receiving interface (I don't need the transmit function so the transm...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

After carefully examine the data from RGMII using signalTap, I found that the data before preamble is "ffff" instead of "ff" (considering DDR). This is 16bits extra data, and I am wondering is it related with IP Payload Alignment to align packet header to 32-bit boundaries?

If the answer is yes, how should I remove this extra data? I tried to select "Align packet headers to 32-bit boundaries" option when I was generating tse MAC in SOPC builder and also tried set bit 25 of "rx_cmd_stat" register to 0 and 1, but no matter what, MAC still indicates this is a frame received with alignment error and then discard it.

I am using Windows XP "ping" command to generate the packet, so does this command generate the extra "ffff" or the Marvell PHY generate "ffff"?