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Altera_Forum
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15 years ago

How to constrain tse on cyclone III board

Hi all, I have a cyclone III board with Marvell 88E1111 RGMII PHY. I am trying to send packet from host to FPGA using RGMII receiving interface (I don't need the transmit function so the transm...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I don't understand either... it is as if the valid signal is asserted one cycle too soon. I agree that it doesn't look like a timing problem. The data valid signal should only be raised by the PHY during the preamble and before the SFD. Not before the preamble.

Can you try the reference design and add the same signaltap probe, and see if you get any different results?