Forum Discussion
Hi,
Sorry for the delay. Regarding the decoder in_ready output, if I understand you correctly, you are referring to this output remains high. For your information, the in_ready is a back-pressure output signal to the source. When the decoder FIFO is almost full, it will de-assert the in_ready to tell the source to stop the data flow.
Regarding the Intel Premier Support, it would be great if you could further engage with your local sales or FAE to further assist you on the account creation.
Please let me know if there is any concern. Thank you.
Chee Pin
- gkash24 years ago
New Contributor
Hi CP Chan,
With your help I was able to proceed further and integrate LDPC IP core in my system. Now the issue which I am facing is that I get errors in Decoded output. Errors occurs in a specific pattern. Pattern is ,mainly starting bits of two adjacent blocks(600/1200 bits fed to ldpc decoder) . Errors occurs rarely, maybe 2 in 100 blocks or so, and I am not able to find the exact reason for it. Data fed to LDPC decoder is same in every block.
Since I have not been able to fully understand exact relation between parameters(number of iterations/parallelism/width of decoder variables/MSA attn. factor) in LDPC decoder, so I tried and experimented. And found that with MSA attenuation factor as 0.25, I get best output with very less errors.
Now, please help me in understanding that why my decoded output is varying rarely. And what is the inter-relation of parameters (number of iterations/parallelism/width of decoder variables/MSA attn. factor) on decoder output?
Info about my project: Quartus Prime Lite Edition 20.1 , Cyclone V ,LDPC(WiMedia 1.5, 600/1200, half rate, itr-50, Par-3, Width-4, MSA AF-0.25) Max input data rate of 16Mbps, Processing frequency is 50Mhz, (1 as 1000 and 0 as 0111, best case).
Enclosed: screenshot of error, error occurs in this pattern only.
Thanks and regards
Gautam