How to compile 2 PCIe instances in one project

Hi dlim

1. 10AX057N3F40E2SG

2. Actually I'm working on big project that in Standard version of quartus compiles well. In the past I used FPGAs that was not supported by pro version (Cyclone V). Before project was accepted I was working on quartus prime 18.1. Now we started this project oficially and updated quartus to pro version. Moving from standard to pro version is a nightmare. I didn't expect such problems at all. My recent post https://community.intel.com/t5/FPGA-Intellectual-Property/Quartus-Pro-v21-1-Synthesis-error-of-two-independent-instance-of/m-p/1271050#M23658 was first problem. We've solved it. Now second problem PCIe.

As a system engineer I wonder about decision of Intel removing bdf editing in pro version of quartus. Of course our projects use system verilog. But top level was always graphical. It is easy to understand the structure of project. Anyway no problem to use as a top of project verilog file. You know better what is the best.

I just simplified my project to have only 2 PCIe devices and get the same error as in my hole project. And it doesn't matter if the top level bdf or verilog. I attach screenshot of 18.1 quartus result and 21.1 pro result of the same hole project. I've tried to compile this project in quartus 20.1.1.170 - result as in 18.1 without any problem.

To understand each other I also attached test project. Idea very simple and I think is clear. Could you please correct this project as it will be able to analysis and synthesis without erros?

Thanks in advance.

Regards,

Pavel