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YYang79's avatar
YYang79
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

How to clock the Cyclone 10GX Transceiver Channel for 10GBASE-R

Hi, In “Intel® Cyclone® 10 GX Transceiver PHY User Guide” at page 100, Fig.44, the tx_clkout is 322.265625 Mhz when select PMA bus width of 32 bits (in picture, it says a number for 40 bit wide bus...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Thanks for your update. For your information, I do not have any insight on the TI's chip and could not really comment on the interop between C10GX and the TI chip. Sorry for the inconvenience.


Just to check with you on the following:

1. Based on your observation that the C10GX RX is missing 64 bits word, would you mind to further elaborate on the observation?


2. What is the IP that you are using in the C10GX device? Native PHY with 10GBase-R mode?


3. Do you observe any anomaly with the XCVR? ie CDR losing lock, rx_ready de-assertion and etc?


4. Just wonder if you have had a chance to perform a serial loopback within the C10GX device to see if you are able to get expected output? This is to help narrow down the issue location and ease debugging.


5. It would be great if you could perform a functional simulation ie in Modelsim to isolate any functional issue before moving to hardware testing.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin



  • YYang79's avatar
    YYang79
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    Thanks for your reply.

    I've tried loopback function of the transceiver locally and found the same issue, missing word or instead of FE...FE word at itself receiver output.

    Yes, I use the IP of 10GBASE-R.

    It looks like the receiving side works well but the transmitting side has problem. I just don't understand quite well about the clocking scheme for TX FIFO. Currently i am using the tx_pma_div_clkout as XGMII interface clock(half of the parallel clock frequency), shown as the attached. Do you think it is a right connection?

    Could it be a problem of PMA stage as well? Do you think that Transceiver Toolkit is helpful to debug my issue? I have never used it before.

    Appreciate a lot and looking forward to your further helps!