Forum Discussion
EBERLAZARE_I_Intel
Regular Contributor
5 years agoHi,
I will look into the issue further, and get back to you with my findings.
EBERLAZARE_I_Intel
Regular Contributor
4 years agoHi,
Communicated via IPS:
The decoding table is attached and the maximum address is 0x3FFF FFFF. User shouldn't writing above this maximum address limit.
Since the end goal is to improve DDR3 performance throughput, and multiple method of changing data pattern address access has been done but still doesn't help, then the only hard way left is to increase DDR3 operating frequency.
However, the board design also must be able to handle higher frequency operation.