Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

How interfacing HPC.II "local_signals" (ddr controller) with vhdl logic ?

Hi, I would like to use the ddr/ddr2 IP HPCII with altmemphy without nios : - HPC 2 full rate, quartus 10.1sp1 - DDR 32MB x16, burst length = 4 (=> local_size=2) My problem is that HPC...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Same questions here. I managed to make it work by doing exactly what's in the official timing diagrams [1], but I don't understand what's going on completely.

I'm pretty sure that the local_xxxs form an Avalon MM interface, the problem is the literature is scarce and misleading [1], [2].

[1] http://www.altera.com/literature/hb/external-memory/emi_altmemphy_ref_timing_diagram.pdf

[2] http://alterawiki.com/wiki/interfacing_to_altera_external_memory_controller_ip

Thanks,

Leo