How interfacing HPC.II "local_signals" (ddr controller) with vhdl logic ?

Hi,

I would like to use the ddr/ddr2 IP HPCII with altmemphy without nios :

- HPC 2 full rate, quartus 10.1sp1

- DDR 32MB x16, burst length = 4 (=> local_size=2)

My problem is that HPC interfacing (local_xxx signals) documentation is very poor. The purpose of every signal is explained (page 454/458) but not how to manage write/read burst operations with these signals. There is only two diagrams (page 494/498) with a very few explanations.

http://www.altera.com/literature/hb/external-memory/emi_archive_101.pdf

I don't know very well ddr devices, so I need more information. Especially I don't understand :

- rows have to be open before write commands with a fake request ?

- write diagram (page 496): why burst_begin is toggling (what about data when burst_begin=0??) and address is incremented only every 2 clk cycle (not when burst_begin=0) ?

- do local_xxx signals respect specific timings ?

- local_data width is 32b => addresses increment is 2 ?

...

Thanks for your help,

Sebastien